Along with the development of manufacturing technologies of displays, Thin Film Transistor-Liquid Crystal Displays (TFT-LCDs) have become predominant in the market due to their small volume, low power consumption, high resolution and other advantages in the market of flat panel displays.
The TFT-LCDs generally include the following two categories dependent upon operating modes of their liquid crystals: one of the categories relates to the liquid crystals operating in a vertical electric field, where a liquid crystal layer is driven by the electric field in the direction substantially perpendicular to the surface of a substrate, and light incident on the liquid crystal layer is modulated for display, and this display mode generally includes a Twisted Nematic (TN) mode, a Multi-domain Vertical Alignment (MVA) mode, etc.; and the other category relates to the liquid crystals operating in a horizontal electric field, where the liquid crystal layer is driven by the electric field in the direction substantially horizontal to the surface of the substrate, and light incident on the liquid crystal layer is modulated for display, and this display mode generally includes an In-Plane Switching (IPS) type, a Fringe Field Switching (FFS) type, etc.
An array substrate is one of main components of a TFT-LCD. the array substrate is prepared in the prior art in a process flow generally including the formation of TFT devices, where the TFT devices are fabricated in a process varying with a different semiconductor material. When the semiconductor material is made of amorphous silicon, TFTs in a bottom-gate structure is typically adopted, and forming the TFT devices includes: forming a gate, a gate insulation layer, a semiconductor layer and a source-drain metal layer in order on the substrate. When the semiconductor material is made of a low-temperature poly-silicon material, TFTs in a top-gate structure are typically adopted, and forming the TFT device includes: forming a semiconductor layer, a gate insulation layer, a gate metal layer, an interlayer dielectric layer and a source-drain metal layer in order on the substrate. A process after the TFT devices are formed slightly varies with a different operating mode of liquid crystals. In the vertical electric field pattern, an interlayer insulation layer and a transparent electrode layer are typically further formed in order on the substrate after the TFT devices are formed. In the horizontal electric field pattern, a passivation layer, a first transparent electrode layer, an interlayer insulation layer and a second transparent electrode layer are typically further formed in order on the substrate after the TFT devices are formed.
In either the vertical electric field pattern or the horizontal electric field pattern, it is typically necessary to form via holes on the insulation layer in a pixel area or an edge area to connect electrically conductive layers on both sides of the insulation layer. The forming the via holes generally includes: forming a photoresist layer on the insulation layer on which the via holes are to be formed; patterning the photoresist layer so that the photoresist layer is provided with a pattern of the via holes to be formed; etching the insulation layer so that the insulation layer with the via holes is formed; and removing the remaining photoresist layer. In the process flow of the array substrate, a lot of charges are accumulated on the substrate due to frictional electrification, contact and separation electrification, inductive electrification and other reasons, and the electrically conductive layer below the insulation layer is exposed in the course of forming the via holes on the insulation layer until forming the conductive layer above the insulation layer; and discharging of electrostatic charges may tend to occur in the processes of stripping away the photoresist, cleaning, etc., so that the TFT devices may be struck or damaged by the electrostatic charges to consequentially come with electrical drifting, so that pixel electrodes may be charged more slowly or rapidly than normal to thereby be lower or higher than a normal pixel potential, thus resulting in a Mura region.